library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;



entity sram_write_mux IS
    GENERIC(
       num_requester      : natural := 4
    );
    PORT( 
       in_sram_wr_addr    : in std_logic_vector((18*num_requester)-1 DOWNTO 0);
       in_sram_wr_data    : in std_logic_vector((16*num_requester)-1 DOWNTO 0);
       
       schedule_nr        : in   std_logic_vector (num_requester-1 DOWNTO 0);
       
       out_sram_wr_addr     : out   std_logic_vector(17 DOWNTO 0);
       out_sram_wr_data     : out   std_logic_vector(15 DOWNTO 0)
    );
end sram_write_mux;



architecture Behavioral of sram_write_mux is
 
    
begin
        

  out_sram_wr_addr <= in_sram_wr_addr(17 downto 0) when schedule_nr = (num_requester-1 downto 1 => '0') & '1' else 
                      in_sram_wr_addr(35 downto 18) when schedule_nr = (num_requester-1 downto 2 => '0') & "10" else
                      (17 downto 0 => '0');

  out_sram_wr_data <= in_sram_wr_data(15 downto 0) when schedule_nr = (num_requester-1 downto 1 => '0') & '1' else
                      in_sram_wr_data(31 downto 16) when schedule_nr = (num_requester-1 downto 2 => '0') & "10" else
                      (15 downto 0 => '0');



end Behavioral;














